capstone

6.0.0-Alpha11

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Capstone disassembly/disassembler framework for ARM, ARM64 (ARMv8), Alpha, BPF, Ethereum VM, HPPA, LoongArch, M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86.
reverse-engineering disassembler security framework arm arm64 x86 sparc powerpc mips x86-64 ethereum systemz webassembly m68k m0s65xx m680x tms320c64x bpf riscv
capstone-engine/capstone

What's New

6.0.0-Alpha11

2026-09-21T17:53:59Z

Highlights

This is another patch release with multiple instruction fixes and bug fixes.

This release adds an AGENTS.md file and developer AI guidelines.

API changes/additions

  • x86: Support alternative disassembly for JO/JNO operands in 64-bit mode.
    This adds two modes for x86: CS_MODE_X86_AMD and CS_MODE_X86_INTEL. Setting either of these flags will
    currently only affect the JO/JNO instructions. Please check the release guide for more details.
    The default behavior of the x86 module did not change.
  • Xtensa: Gate ESP32-S3 and HIFI3 instructions behind CS_MODE_XTENSA_ESP32S3

New instruction

  • PowerPC: add mcrxr instruction support

Instruction fixes

  • AArch64: report NZCV access for MRS/MSR of NZCV
  • HHPA: Correct name of r0 register - flags -> r0
  • x86: use effective address size for the loop counter register
  • x86: fix VMOVUPS memory operand access
  • PowerPC: Keep BI out of the CTR-only branch predicate
  • x86: fix EVEX writemask access in AT&T syntax

What's Changed

  • Xtensa: gate ESP32-S3 and HIFI3 ops behind CS_MODE_XTENSA_ESP32S3 by @germiBest in #2979
  • AArch64: report NZCV access for MRS/MSR of NZCV by @gaul in #3002
  • xtensa: sign-extend scaled offsets in decodeOffset_* helpers by @Samin061 in #2997
  • Fix Xtensa test with wrong mode selection. by @Rot127 in #3004
  • Xtensa: Fix Stack overflow by @Rot127 in #3012
  • AArch64: Fix diet-mode NULL deref in printMatrixTileVector by @amit-sides in #3017
  • HHPA: Correct name of r0 register - flags -> r0 by @Rot127 in #3024
  • Fix read from uninitialized memory by @Rot127 in #3011
  • Add MSAN build option to CMakeLists.txt by @Rot127 in #3029
  • x86: use effective address size for the loop counter register by @phverg in #3025
  • systemz: bounds-check register index in decodeRegisterClass by @jmestwa-coder in #3044
  • x86: fix VMOVUPS memory operand access by @raaller in #3035
  • PowerPC: Keep BI out of the CTR-only branch predicate by @phix33 in #3043
  • Alpha: Fix implicit read/write details for some memory instructions by @atirna in #3034
  • X86: Fix four AT&T operand-detail defects by @phix33 in #3042
  • RISCV: Revamp flags to allow fine grained control over aliasing by @moste00 in #3008
  • M68K: Fix fmove.x 96-bit extended immediate decode length and printing by @b1llow in #3016
  • AArch64: fix Rt operand of the integer STLUR forms by @gaul in #3046
  • AArch64: SYSL writes its Rt operand, it does not read it by @gaul in #3045
  • x86: fix near RET decoding with 0x66 and REX.W by @raaller in #3049
  • ARM/AArch64: Improve runtime of ARM/AArch64 register name patching. by @Rot127 in #3048
  • Handle case of vsprintf returning oob pointer offset. by @Rot127 in #3060
  • PowerPC: add mcrxr instruction support by @StilesCrisis in #3065
  • X86: Zero the operand slot before filling it in the Intel implicit insert by @phix33 in #3057
  • cstest: Compare the PPC branch details once and without requiring operands by @phix33 in #3058
  • Add AI guidelines and requirements. by @Rot127 in #3064
  • x86: Add missing access info for operand[3] of vmulps. by @raaller in #3059
  • x86: fix EVEX writemask access in AT&T syntax by @raaller in #3072
  • Replace all system allocations with cs_mem_ allocations. by @Rot127 in #3074
  • x86: fix JO/JNO operand size in 64-bit mode by @raaller in #3067
  • riscv: propagate register-class decode failure in custom decoders by @jmestwa-coder in #3071
  • x86: Fix access of X86_CMPSL memory operands by @raaller in #3080
  • Add AI guidance by @raaller in #3081

New Contributors

Full Changelog: 6.0.0-Alpha10...6.0.0-Alpha11

Switch from v5 to v6

Please check out our release guide to get an overview what changed, improved, and how the transition can be made as painless as possible: https://github.com/capstone-engine/capstone/blob/next/docs/cs_v6_release_guide.md

Capstone Engine

Build status pypi package pypi downloads oss-fuzz Status

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Welcome to join our community group!  

Capstone is a disassembly framework with the target of becoming the ultimate disasm engine for binary analysis and reversing in the security community.

Created by Nguyen Anh Quynh, then developed and maintained by a small community, Capstone offers some unparalleled features:

  • Support multiple hardware architectures: ARM, AArch64, Alpha, ARC, BPF, Ethereum VM, LoongArch, HP PA-RISC (HPPA), M68K, M680X, Mips, MOS65XX, PPC, RISC-V(rv32G/rv64G), SH, Sparc, SystemZ, TMS320C64X, TriCore, Webassembly, XCore and X86 (16, 32, 64), Xtensa.

  • Having clean/simple/lightweight/intuitive architecture-neutral API.

  • Provide details on disassembled instruction (called “decomposer” by others).

  • Provide semantics of the disassembled instruction, such as list of implicit registers read & written.

  • Implemented in pure C language, with lightweight bindings for Swift, D, Clojure, F#, Common Lisp, Visual Basic, PHP, PowerShell, Emacs, Haskell, Perl, Python, Ruby, C#, NodeJS, Java, GO, C++, OCaml, Lua, Rust, Delphi, Free Pascal & Vala ready either in main code, or provided externally by the community).

  • Native support for all popular platforms: Windows, Mac OSX, iOS, Android, Linux, *BSD, Solaris, etc.

  • Thread-safe by design.

  • Special support for embedding into firmware or OS kernel.

  • High performance & suitable for malware analysis (capable of handling various X86 malware tricks).

  • Distributed under the open source BSD license.

Further information is available at https://www.capstone-engine.org

Compile

See BUILDING.md file for how to compile and install Capstone.

Documentation

Contributing

See CONTRIBUTING.md for an intro.

Fuzz

See suite/fuzz/README.md for more information.

License

This project is released under the BSD license. If you redistribute the binary or source code of Capstone, please attach file LICENSE.TXT with your products.

Description

  • Swift Tools
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Dependencies

  • None
Last updated: Mon Nov 02 2026 00:19:26 GMT-1000 (Hawaii-Aleutian Standard Time)